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Deep reactive-ion etching of Silicon, or Deep Silicon Etching, is a highly anisotropic etch process used to create deep, steep-sided holes and trenches in wafers/substrates, typically with high aspect ratios.
Deep Silicon Etch (DSiE) solutions serve a diverse set of process requirements across the Micro Electro Mechanical Systems (MEMS), Advanced Packaging and Nanotechnology markets.
The two technologies used to achieve deep etches in the fabrication of micro-electro-mechanical systems (MEMS) are the Bosch and the Cryogenic Processes. System and process development over many years has allowed the techniques to advance but the fundamental aspects of each remain the same:
Designed to enable the fabrication of all Si etch devices, Deep Silicon Etching delivers:
The Bosch process uses a fluorine based plasma chemistry to etch the silicon, combined with a fluorocarbon plasma process to provide sidewall passivation and improved selectivity to etch mask. A complete etch process cycles between etch and deposition steps many times to achieve deep, vertical etch profiles. It relies on the source gases being broken down in a high-density plasma region before reaching the wafer.
This technique cannot be performed in reactive ion etch systems (RIE), as these have the wrong balance of ions to free radical species. This balance can be achieved in high-density plasma systems (HDP). The most widely used form of HDP uses inductive coupling to generate the high-density plasma region so is known as ‘inductively coupled plasma’ (ICP).
High rate, controlled scallops e.g. Microfluidics (200mm depth), vias (> 400 mm depth)
Microneedles created using the Bosch process
Just as for the Bosch process, this technique also uses SF6 to provide fluorine radicals for silicon etching. The silicon is removed in the form of SiF4, which is volatile.
The main difference is in the mechanism of sidewall passivation and mask protection. Rather than using a fluorocarbon polymer, this process relies on forming a blocking layer of oxide/fluoride (SiOxFy) on the sidewalls (around 10-20nm thick), this forms at the cryogenic temperatures used and the layer inhibits the attack on the underlying Si layer by the fluorine radicals.
The low temperature and low bias operation also assists in reducing the etch rate of the mask material, which is normally either photoresist or silicon dioxide.
Micro-mould created using the Cryo process
Si waveguide etch
Smooth sidewall cryogenic DSE (no scallops).
Courtesy TU Twente
PlasmaPro 100 Estrelas provides total flexibility for Deep Silicon Etch (DSiE) applications which is applied across across the Micro Electro Mechanical Systems (MEMS), Advanced Packaging and Nanotechnology markets.